This invention relates generally to semiconductor-on-insulator transistors, DRAM and other circuitry employing semiconductor-on-insulator transistors, methods of forming a semiconductor-on-insulator transistors, and methods of forming memory circuitry employing semiconductor-on-insulator transistors.
Field effect transistors are typically comprised of a pair of diffusion regions, typically referred to as a source and a drain, spaced apart within a semiconductor substrate. Such include a gate provided adjacent to a separation region between the diffusion regions for imparting an electric field to enable current to flow between the diffusion regions. The substrate area adjacent the gate in between the diffusion regions is referred to as the channel.
The semiconductive substrate typically comprises a bulk monocrystalline silicon substrate having a light conductivity dopant impurity concentration. The diffusion regions typically have a considerably higher dopant concentration of a conductivity enhancing impurity of an opposite type. Alternately, the substrate can be provided in the form of a thin layer of lightly doped semiconductive material over an underlying insulator layer. Such are commonly referred to a semiconductor-on-insulator (SOI) constructions. The diffusion regions in SOI constructions can extend completely through the thin silicon layer, which is commonly referred to as a fully depleted SOI construction. Alternately, the diffusion regions may extend only partially into or through the thickness of the thin silicon layer, something which is commonly referred to as partially depleted SOI constructions. Regardless, a conductive gate is positioned either above or below the SOI layer to provide gating between the diffusion regions in a transistor which is substantially horizontally oriented.
Field effect transistors constitute one common type of electronic device or component utilized in integrated circuitry. High density integrated circuitry is principally fabricated from semiconductor wafers. Upon fabrication completion, a wafer contains a plurality of identical discrete die areas which are ultimately cut from the wafer to form individual chips. Die areas or cut dies are tested for operability, with good dies being assembled into encapsulating packages which are used in end-products or systems.
One type of integrated circuitry comprises memory. The basic unit of semiconductor memory is the memory cell. Capable of storing a single bit of information, the memory cell has steadily shrunk in size to enable more and more cells per area of a semiconductor substrate or wafer. Such enables integrated memory circuitry to be more compact, as well as faster in operation.
Example semiconductor memories include ROMs, RAMs, PROMs, EPROMs, and EEPROMs. Some emphasize compactness and economy over speed. Other focus on lightening-fast operation. Some store data indefinitely, while others are so temporary they must be refreshed hundreds of times every second. One of the smallest memory cells comprises the single transistor and single capacitor of a dynamic random access memory (DRAM).